The Design and Implementation of a Large-Scale Placer Based on Grid-Warping

Placement is an important step in the overall IC design process, as it defines the on-chip interconnects, which are the bottleneck in determining circuit performance. Grid-warping is a new placement algorithm based on a strikingly simple idea: rather than move the gates to optimize their location, we elastically deform a model of the 2-D chip surface on which the gates have been roughly placed, “stretching” it until the gates arrange themselves to our liking. Put simply: we move the gird, not the gates. Deforming the elastic grid is a surprisingly simple, low-dimensional nonlinear optimization, and augments a traditional quadratic formulation. We describe in detail the algorithm design and detailed engineering of the first large-scale grid-warping placer capable of handling industrial-size designs with a mix of macrocells and gates. Experimental results show that our implementation of these ideas, a sequence of placers called WARP1, WARP2 and WARP3, are competitive with most recently published placers.